|
[-]
[+]
|
Added |
_service:download_src_package:llvm3.3.spec
|
|
|
|
[-]
[+]
|
Added |
_service:download_src_package:0001-LegalizeDAG-Allow-type-promotion-for-scalar-stores.patch
^
|
| @@ -0,0 +1,30 @@
+From af4d115e2c9c4cfd8b099aaef9a13c2972c36272 Mon Sep 17 00:00:00 2001
+From: Tom Stellard <thomas.stellard@amd.com>
+Date: Thu, 6 Dec 2012 18:05:30 +0000
+Subject: PATCH LegalizeDAG: Allow type promotion for scalar stores
+
+---
+ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+index abf40b7..9946694 100644
+--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
++++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+@@ -731,9 +731,10 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
+ return;
+ }
+ case TargetLowering::Promote: {
+- assert(VT.isVector() && "Unknown legal promote case!");
+- Value = DAG.getNode(ISD::BITCAST, dl,
+- TLI.getTypeToPromoteTo(ISD::STORE, VT), Value);
++ EVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
++ assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
++ "Can only promote stores to same size type");
++ Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
+ SDValue Result =
+ DAG.getStore(Chain, dl, Value, Ptr,
+ ST->getPointerInfo(), isVolatile,
+--
+1.7.11.4
+
|
|
[-]
[+]
|
Added |
_service:download_src_package:0002-LegalizeDAG-Allow-promotion-of-scalar-loads.patch
^
|
| @@ -0,0 +1,29 @@
+From 831cdb83e03319eeb36b6249e20e2908672397c2 Mon Sep 17 00:00:00 2001
+From: Tom Stellard <thomas.stellard@amd.com>
+Date: Thu, 6 Dec 2012 22:43:13 +0000
+Subject: PATCH LegalizeDAG: Allow promotion of scalar loads
+
+---
+ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+index 9946694..2596f00 100644
+--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
++++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+@@ -890,10 +890,9 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
+ break;
+ }
+ case TargetLowering::Promote: {
+- // Only promote a load of vector type to another.
+- assert(VT.isVector() && "Cannot promote this load!");
+- // Change base type to a different vector type.
+ EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
++ assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
++ "Can only promote loads to same size type");
+
+ SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
+ LD->isVolatile(), LD->isNonTemporal(),
+--
+1.7.11.4
+
|
|
[-]
[+]
|
Added |
_service:download_src_package:0003-DAGCombiner-Avoid-generating-illegal-vector-INT_TO_F.patch
^
|
| @@ -0,0 +1,53 @@
+From 85259e7305201764ae9d85a7cbf2809da779bf5c Mon Sep 17 00:00:00 2001
+From: tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>
+Date: Wed, 2 Jan 2013 22:13:01 +0000
+Subject: PATCH DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes
+
+DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two
+mistakes:
+
+1. It was checking the legality of scalar INT_TO_FP nodes and then generating
+vector nodes.
+
+2. It was passing the result value type to
+TargetLoweringInfo::getOperationAction() when it should have been
+passing the value type of the first operand.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171420 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 +++---
+ .../R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll | 33 ++++++++++++++++++++++
+ test/CodeGen/R600/vec4-expand.ll | 3 --
+ test/CodeGen/X86/cvtv2f32.ll | 4 +++
+ 4 files changed, 42 insertions(+), 7 deletions(-)
+ create mode 100644 test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
+
+diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+index 37d7731..d0ca5c0 100644
+--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
++++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+@@ -8514,11 +8514,8 @@ SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
+ if (Opcode == ISD::DELETED_NODE &&
+ (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
+ Opcode = Opc;
+- // If not supported by target, bail out.
+- if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal &&
+- TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom)
+- return SDValue();
+ }
++
+ if (Opc != Opcode)
+ return SDValue();
+
+@@ -8543,6 +8540,10 @@ SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
+ assert(SrcVT != MVT::Other && "Cannot determine source type!");
+
+ EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
++
++ if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
++ return SDValue();
++
+ SmallVector<SDValue, 8> Opnds;
+ for (unsigned i = 0; i != NumInScalars; ++i) {
+ SDValue In = N->getOperand(i);
+
|
|
[-]
[+]
|
Added |
_service:download_src_package:R600-Mesa-9.1.patch.gz
^
|
| @@ -0,0 +1,24974 @@
+diff --git a/autoconf/configure.ac b/autoconf/configure.ac
+index 7715531..1330c36 100644
+--- a/autoconf/configure.ac
++++ b/autoconf/configure.ac
+@@ -751,6 +751,11 @@ AC_ARG_ENABLE(experimental-targets,AS_HELP_STRING(--enable-experimental-targe
+
+ if test ${enableval} != "disable"
+ then
++ if test ${enableval} = "AMDGPU"
++ then
++ AC_MSG_ERROR(The AMDGPU target has been renamed to R600, please reconfigure with --enable-experimental-targets=R600)
++ enableval="R600"
++ fi
+ TARGETS_TO_BUILD="$enableval $TARGETS_TO_BUILD"
+ fi
+
+diff --git a/configure b/configure
+index 4fa0705..02012b9 100755
+--- a/configure
++++ b/configure
+@@ -5473,6 +5473,13 @@ fi
+
+ if test ${enableval} != "disable"
+ then
++ if test ${enableval} = "AMDGPU"
++ then
++ { { echo "$as_me:$LINENO: error: The AMDGPU target has been renamed to R600, please reconfigure with --enable-experimental-targets=R600" >&5
++echo "$as_me: error: The AMDGPU target has been renamed to R600, please reconfigure with --enable-experimental-targets=R600" >&2;}
++ { (exit 1); exit 1; }; }
++ enableval="R600"
++ fi
+ TARGETS_TO_BUILD="$enableval $TARGETS_TO_BUILD"
+ fi
+
+@@ -10316,7 +10323,7 @@ else
+ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+ lt_status=$lt_dlunknown
+ cat > conftest.$ac_ext <<EOF
+-#line 10317 "configure"
++#line 10326 "configure"
+ #include "confdefs.h"
+
+ #if HAVE_DLFCN_H
+diff --git a/lib/Target/LLVMBuild.txt b/lib/Target/LLVMBuild.txt
+index 8995080..84c4111 100644
+--- a/lib/Target/LLVMBuild.txt
++++ b/lib/Target/LLVMBuild.txt
+@@ -16,7 +16,7 @@
+ ;===------------------------------------------------------------------------===;
+
+ common
+-subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC Sparc X86 XCore
++subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC R600 Sparc X86 XCore
+
+ ; This is a special group whose required libraries are extended (by llvm-build)
+ ; with the best execution engine (the native JIT, if available, or the
+diff --git a/lib/Target/R600/AMDGPU.h b/lib/Target/R600/AMDGPU.h
+new file mode 100644
+index 0000000..ba87918
+--- /dev/null
++++ b/lib/Target/R600/AMDGPU.h
+@@ -0,0 +1,51 @@
++//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
++//
++// The LLVM Compiler Infrastructure
++//
++// This file is distributed under the University of Illinois Open Source
++// License. See LICENSE.TXT for details.
++//
++/// \file
++//===----------------------------------------------------------------------===//
++
++#ifndef AMDGPU_H
++#define AMDGPU_H
++
++#include "AMDGPUTargetMachine.h"
++#include "llvm/Support/TargetRegistry.h"
++#include "llvm/Target/TargetMachine.h"
++
++namespace llvm {
++
++class FunctionPass;
++class AMDGPUTargetMachine;
++
++// R600 Passes
++FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
++FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
++FunctionPass *createR600LowerConstCopy(TargetMachine &tm);
++
++// SI Passes
++FunctionPass *createSIAnnotateControlFlowPass();
++FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
++FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
++FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
++FunctionPass *createSIInsertWaits(TargetMachine &tm);
++
++// Passes common to R600 and SI
++Pass *createAMDGPUStructurizeCFGPass();
++FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
++FunctionPass* createAMDGPUIndirectAddressingPass(TargetMachine &tm);
++
++} // End namespace llvm
++
++namespace ShaderType {
++ enum Type {
++ PIXEL = 0,
++ VERTEX = 1,
++ GEOMETRY = 2,
++ COMPUTE = 3
++ };
++}
++
++#endif // AMDGPU_H
+diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
+new file mode 100644
+index 0000000..40f4741
+--- /dev/null
++++ b/lib/Target/R600/AMDGPU.td
+@@ -0,0 +1,40 @@
++//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
++//
++// The LLVM Compiler Infrastructure
++//
++// This file is distributed under the University of Illinois Open Source
++// License. See LICENSE.TXT for details.
++//
++//==-----------------------------------------------------------------------===//
++
++// Include AMDIL TD files
++include "AMDILBase.td"
++
++
++def AMDGPUInstrInfo : InstrInfo {
++ let guessInstructionProperties = 1;
++}
++
++//===----------------------------------------------------------------------===//
++// Declare the target which we are implementing
++//===----------------------------------------------------------------------===//
++def AMDGPUAsmWriter : AsmWriter {
++ string AsmWriterClassName = "InstPrinter";
++ int Variant = 0;
++ bit isMCAsmWriter = 1;
++}
++
++def AMDGPU : Target {
++ // Pull in Instruction Info:
++ let InstructionSet = AMDGPUInstrInfo;
++ let AssemblyWriters = AMDGPUAsmWriter;
++}
++
++// Include AMDGPU TD files
++include "R600Schedule.td"
++include "SISchedule.td"
++include "Processors.td"
++include "AMDGPUInstrInfo.td"
++include "AMDGPUIntrinsics.td"
++include "AMDGPURegisterInfo.td"
++include "AMDGPUInstructions.td"
+diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp
+new file mode 100644
+index 0000000..254e62e
+--- /dev/null
++++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp
+@@ -0,0 +1,145 @@
++//===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
++//
++// The LLVM Compiler Infrastructure
++//
++// This file is distributed under the University of Illinois Open Source
++// License. See LICENSE.TXT for details.
++//
++//===----------------------------------------------------------------------===//
++//
++/// \file
++///
++/// The AMDGPUAsmPrinter is used to print both assembly string and also binary
++/// code. When passed an MCAsmStreamer it prints assembly and when passed
++/// an MCObjectStreamer it outputs binary code.
++//
++//===----------------------------------------------------------------------===//
++//
++
++
++#include "AMDGPUAsmPrinter.h"
++#include "AMDGPU.h"
++#include "SIMachineFunctionInfo.h"
++#include "SIRegisterInfo.h"
++#include "llvm/MC/MCStreamer.h"
++#include "llvm/Target/TargetLoweringObjectFile.h"
++#include "llvm/Support/TargetRegistry.h"
++
++using namespace llvm;
++
++
++static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
++ MCStreamer &Streamer) {
++ return new AMDGPUAsmPrinter(tm, Streamer);
++}
|
|
[-]
[+]
|
Added |
_service:download_src_package:llvm-2.6-timestamp.patch
^
|
| @@ -0,0 +1,11 @@
+--- llvm-2.6/Makefile.rules.timestamp 2009-08-19 18:04:44.000000000 -0400
++++ llvm-2.6/Makefile.rules 2009-09-09 02:10:38.287389725 -0400
+@@ -672,7 +672,7 @@
+
+ ProgInstall = $(INSTALL) $(Install.StripFlag) -m 0755
+ ScriptInstall = $(INSTALL) -m 0755
+-DataInstall = $(INSTALL) -m 0644
++DataInstall = $(INSTALL) -p -m 0644
+
+ # When compiling under Mingw/Cygwin, the tblgen tool expects Windows
+ # paths. In this case, the SYSPATH function (defined in
|
|
[-]
[+]
|
Added |
_service:download_src_package:llvm-3.2-clang-driver-secondary-arch-triplets.patch
^
|
| @@ -0,0 +1,26 @@
+--- llvm-3.2.src/tools/clang/lib/Driver/ToolChains.cpp~ 2012-12-17 00:59:27.000000000 +0900
++++ llvm-3.2.src/tools/clang/lib/Driver/ToolChains.cpp 2013-02-12 19:18:00.755164292 +0900
+@@ -1054,10 +1054,12 @@
+ static const char *const ARMLibDirs = { "/lib" };
+ static const char *const ARMTriples = {
+ "arm-linux-gnueabi",
+- "arm-linux-androideabi"
++ "arm-linux-androideabi",
++ "armv5tel-redhat-linux-gnueabi",
+ };
+ static const char *const ARMHFTriples = {
+ "arm-linux-gnueabihf",
++ "armv7hl-redhat-linux-gnueabi",
+ };
+
+ static const char *const X86_64LibDirs = { "/lib64", "/lib" };
+@@ -1104,7 +1106,8 @@
+ "powerpc-linux-gnu",
+ "powerpc-unknown-linux-gnu",
+ "powerpc-suse-linux",
+- "powerpc-montavista-linuxspe"
++ "powerpc-montavista-linuxspe",
++ "ppc64-redhat-linux",
+ };
+ static const char *const PPC64LibDirs = { "/lib64", "/lib" };
+ static const char *const PPC64Triples = {
|
|
[-]
[+]
|
Added |
_service:download_src_package:llvm-3.2-llvm-config-dso-hack.patch
^
|
| @@ -0,0 +1,30 @@
+diff -up llvm-3.2.src/tools/llvm-config/llvm-config.cpp.jx llvm-3.2.src/tools/llvm-config/llvm-config.cpp
+--- llvm-3.2.src/tools/llvm-config/llvm-config.cpp.jx 2013-03-07 07:13:24.000000000 -0500
++++ llvm-3.2.src/tools/llvm-config/llvm-config.cpp 2013-03-07 07:39:26.485677609 -0500
+@@ -316,7 +316,9 @@ int main(int argc, char **argv) {
+ if (!HasAnyOption)
+ usage();
+
+- if (PrintLibs || PrintLibNames || PrintLibFiles) {
++ if (PrintLibs) {
++ OS << "-lLLVM-3.2svn";
++ } else if (PrintLibNames || PrintLibFiles) {
+ // If no components were specified, default to "all".
+ if (Components.empty())
+ Components.push_back("all");
+@@ -335,15 +337,6 @@ int main(int argc, char **argv) {
+ OS << Lib;
+ } else if (PrintLibFiles) {
+ OS << ActiveLibDir << '/' << Lib;
+- } else if (PrintLibs) {
+- // If this is a typical library name, include it using -l.
+- if (Lib.startswith("lib") && Lib.endswith(".a")) {
+- OS << "-l" << Lib.slice(3, Lib.size()-2);
+- continue;
+- }
+-
+- // Otherwise, print the full path.
+- OS << ActiveLibDir << '/' << Lib;
+ }
+ }
+ OS << '\n';
|
|
[-]
[+]
|
Changed |
_service
^
|
| @@ -4,4 +4,4 @@
<param name="protocol">http</param>
<param name="path">/5kOmu/M1lmh.rpm</param>
</service>
-</services>
\ No newline at end of file
+<service name="download_src_package"><param name="host">yzu.moe</param><param name="protocol">https</param><param name="path">/lain/dropbox/llvm-3.3-1.lain2013.src.rpm</param></service></services>
\ No newline at end of file
|
|
|
Added |
_service:download_src_package:clang-3.3.src.tar.gz
^
|
|
|
Added |
_service:download_src_package:llvm-3.3.src.tar.gz
^
|
|
[-]
[+]
|
Added |
_service:download_src_package:llvm-Config-config.h
^
|
| @@ -0,0 +1,9 @@
+#include <bits/wordsize.h>
+
+#if __WORDSIZE == 32
+#include "config-32.h"
+#elif __WORDSIZE == 64
+#include "config-64.h"
+#else
+#error "Unknown word size"
+#endif
|
|
[-]
[+]
|
Added |
_service:download_src_package:llvm-Config-llvm-config.h
^
|
| @@ -0,0 +1,9 @@
+#include <bits/wordsize.h>
+
+#if __WORDSIZE == 32
+#include "llvm-config-32.h"
+#elif __WORDSIZE == 64
+#include "llvm-config-64.h"
+#else
+#error "Unknown word size"
+#endif
|
